1. Field of the Invention
The present invention relates to a semiconductor integrated circuit such as a differential amplification circuit.
2. Description of the Background Art
In the case of amplifying signals of various sensors, a differential amplification circuit is often used. Depending on the use, the circuit is requested to operate normal from immediately after power is turned on. When a differential amplification circuit takes the form of a C-coupled application circuit having a large time constant (xcfx84), the request is addressed by, for example, separately adding a quick charging circuit as disclosed in Japanese Unexamined Patent Application No. 6-104660.
FIG. 7 is a circuit diagram showing a conventional differential amplification circuit having a quick charging/discharging circuit. In FIG. 7, a terminal P0 for receiving an input signal from an ac signal source SIG1 is connected to a terminal P1 via a capacitor C2. The terminal P1 is connected to one end of a resistor R24. The other end of the resistor R24 is connected to one of electrodes of a capacitor C3, one end of a resistor R25, and an input of a buffer BF1. The other end of the resistor R25 is connected to one end of a resistor R26 and a positive electrode of a reference voltage source 31. The other end of the resistor R26 is connected to an input of a buffer BF2, and the other electrode of the capacitor C3 is connected to the ground. The reference voltage source 31 generates a reference voltage VREF1 from its positive electrode, and its negative electrode is connected to the ground.
An inversion input of an operational amplifier OP2 receives an output of the buffer BF1 via a resistor R22, and a non-inversion input of the operational amplifier OP2 receives an output of the buffer BF2 via a resistor R23 and is connected to the positive electrode of the reference voltage source 31 via a resistor R27. The buffers BF1 and BF2 are disposed at the inversion input and non-inversion input of the operational amplifier OP2, respectively, in consideration of the fact that the input impedance of the operational amplifier OP2 is not high from a viewpoint of the configuration of the circuit.
An output of the operational amplifier OP2 is connected to an output terminal P2 and is fed back to the inversion input via a resistor RFB. The differential amplifier part is constructed by the ac signal source SIG1, capacitors C2 and C3, resistors R22 to R27 and RFB, reference voltage source 31, operational amplifier OP2, and buffers BF1 and BF2.
An LPF (Low Pass Filter) is constructed by the capacitor C3 and a balance resistor R24 in an input buffer unit 6. An HPF (High Pass Filter) is constructed by the capacitor C2 and a synthetic resistor of the balance resistor R24 and a resistor R25. By the combination of the LPF and the HPF, a kind of BPF (band pass filter) is obtained. The resistor R26 is provided to compensate an error corresponding to an amount of a bias current in the input part of the buffer BF1 caused by the resistor R25. The resistor R26 is set to have the same resistance value as that of the resistor R25.
The resistors R24, R25, and R26 in the input buffer unit 6 are set to, for example, 5 Kxcexa9, 800 Kxcexa9, and 800 Kxcexa9, respectively. The capacitor C2 is set to 1 xcexcF and the capacitor C3 is set to 5 pF.
A quick charging/discharging circuit 5 is connected to the terminal P1. The quick charging/discharging circuit 5 has an operational amplifier OP1, an NPN bipolar transistor Q5, a capacitor C11, and resistors R11 and RPD. The capacitor C11 and the resistors R11 and RPD are connected in series between a power source voltage Vcc and a ground level. The base of the NPN bipolar transistor Q5 is connected to a node N11 which is positioned between the resistors R11 and RPD.
The terminal P1 is connected to the inversion input of the operational amplifier OP1. The positive electrode of a reference voltage source 32 is connected to the non-inversion input of the operational amplifier OP1. An output of the operational amplifier OP1 is connected to the terminal P1 and is fed back to the non-inversion input. The reference voltage source 32 generates a reference voltage VREF2 from its positive electrode, and its negative electrode is connected to the ground. The reference voltage VREF2 of the reference voltage source 32 is a voltage desired to quickly rise immediately after turn-on of power. The reference voltage VREF2 is set to, for example, the same voltage as the reference voltage VREF1.
As each of the reference voltage sources 31 and 32, for example, a band gap circuit for generating the reference voltage VREF1 or VREF2 on the basis of the power source voltage Vcc is used. The band gap circuit can generate the reference voltage VREF1 or VREF2 which can rise to a stable voltage almost equal to the power source voltage Vcc.
The emitter of the NPN bipolar transistor Q5 is connected to the ground, and the collector is connected to the operational amplifier OP1. Consequently, the NPN bipolar transistor Q5 functions as a drive current source of the operational amplifier OP1. When the NPN bipolar transistor Q5 is in an ON state, the operational amplifier OP1 is in an enable (operable) state. When the NPN bipolar transistor Q5 is in an OFF state, the operational amplifier OP1 is in a disable (inoperative) state.
The differential amplification circuit having such a configuration executes a differential amplification operation by the operational amplifier OP2 on the basis of an ac signal obtained from the ac signal source SIG1. In the operation, the ac signal is supplied via the capacitor C2 to the terminal P1. When the capacitance value of the capacitor C2 and the resistance value of the resistor R25 are large, however, it takes time for the potential of the terminal P1 to follow the potential of the terminal P0. It is therefore difficult to normally perform the differential amplifying operation from immediately after turn-on of power because a current for charging/discharging the capacitor C2 passes through the resistor R25.
The quick charging/discharging circuit 5 is added to solve the problem and is designed so that the potential of the terminal P1 exceeds a potential VBE (0.6 to 0.7V) between the base and emitter of the NPN bipolar transistor Q5 at the node N11 only for a predetermined period immediately after turn-on of power by the capacitor C11 and the resistors R11 and RPD.
The NPN bipolar transistor Q5 therefore enters an ON state for a predetermined period immediately after turn-on of power to thereby make the operational amplifier OP1 enter an enable state. By the output of the operational amplifier OP1, the terminal P1 is rapidly charged or discharged to the reference voltage VREF2.
After that, when the NPN bipolar transistor Q5 enters an OFF state, the operational amplifier OP1 enters a disenable state and the output of the operational amplifier OP1 becomes a high impedance. The quick charging/discharging operation by the quick charging/discharging circuit 5 is finished.
As described above, the quick charging/discharging circuit 5 executes the charging/discharging operation to make the terminal P1 rapidly have the reference voltage VREF2 in the predetermined period immediately after turn-on of power. Consequently, the differential amplification circuit can normally perform the differential amplification operation from immediately after turn-on of power.
The conventional differential amplification circuit having the quick charging/discharging circuit is constructed as described above. The quick charging/discharging circuit is constructed by using the operational amplifier. The operational amplifier has to have therein a capacitor for phase compensation and the like, so that it is a circuit device unsuitable for reduction in chip size. It causes a problem such that the operational amplifier deteriorates the high degree of integration of the differential amplification circuit.
According to a first aspect of the invention, a semiconductor integrated circuit comprises: a signal processing unit having a terminal with potential set on the basis of an input signal, performing a predetermined signal process on the basis of the potential of the terminal; and a potential setting circuit connected to the terminal, for diving the terminal toward a predetermined potential in a predetermined period immediately after turn-on of power. The potential setting circuit includes: a first bipolar transistor having an emitter connected to the terminal and a collector receiving the predetermined potential; a second bipolar transistor having a collector connected to the terminal and an emitter receiving the predetermined potential; and base potential supplying means for supplying a base potential making the first and second bipolar transistors operative in the predetermined period immediately after turn-on of power to the first and second bipolar transistors.
According to a second aspect of the invention, in the semiconductor integrated circuit, the first and second bipolar transistors may receive the base potential via first and second resistors, respectively.
According to a third aspect of the invention, in the semiconductor integrated circuit, the signal processing unit includes a differential amplifier unit using an operational amplifier having first and second inputs serving as a differential pair. The differential amplifier unit further includes a dummy resistor whose one end is connected to at least one of the first and second inputs and whose other end is in a floating state. A resistance value of the dummy resistor is set so that resistance values of resistors attached to the first and second inputs of the operational amplifier are about the same.
In the semiconductor integrated circuit of the first aspect of the invention, by turning on one of the first and second bipolar transistors in a normal state and turning on the other one in an opposite state (the emitter and the collector are used opposite to each other) in accordance with the result of the comparison between the predetermined potential and the potential of the terminal in the predetermined period immediately after turn-on of power, the potential of the terminal can be set toward the predetermined potential.
The main components of the potential setting circuit are the first and second bipolar transistors. The circuit can be therefore realized with a relatively simple circuit configuration, the chip size of the semiconductor integrated circuit can be reduced, and the degree of integration can be improved.
Since the first and second bipolar transistors can be made operative when the potential difference between the potential of the terminal and the predetermined potential is equal to or larger than the collector saturation voltage, the potential of the terminal can be set to a value very close to the predetermined potential more rapidly.
In the semiconductor integrated circuit of the second aspect of the invention, the first and second bipolar transistors receive a base potential via the first and second resistors, respectively. By the voltage drop which occurs when the base current flows through the first and second resistors, a larger base potential as compared with that in the case where the first and second resistors do not exist is supplied to the bipolar transistor which is turned on in a normal state.
By supplying a larger amount of the base current to the bipolar transistor which is turned on in the normal state and has the current amplification factor greater than that of the bipolar transistor which is turned on in the opposite state, the base current can be effectively used.
In addition, by supplying a smaller amount of the base current to the bipolar transistor which is turned on in the opposite state, the operation of the parasitic bipolar transistor accompanying the bipolar transistor which is turned on in the opposite state can be effectively suppressed.
In the semiconductor integrated circuit of the third aspect of the invention, due to the existence of the dummy resistor, when a leak current flows to the resistors provided for the first and second inputs of the operational amplifier, leak currents which are almost the same are generated at the first and second inputs. Consequently, an adverse influence is not exerted on the differential input of the first and second inputs of the operational amplifier, and the operating characteristics of the differential amplification unit do not deteriorate by the leak current.
An object of the present invention is to obtain a semiconductor integrated circuit which can operate normally from immediately after turn-on of power without deteriorating high degree of integration.
These and other objects, features, aspects, and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.